1. Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a nonvolatile semiconductor memory device and a semiconductor device including the semiconductor memory device. Furthermore, this invention also relates to a device, such as an electronic device, which includes the semiconductor device mentioned above.
2. Description of the Related Art
In recent years, as a semiconductor memory device, other than a volatile memory which loses its data when power supply is turned off, there are proposed various types of nonvolatile semiconductor memories which can hold stored data even if power supply is turned off. For instance, as this type of nonvolatile semiconductor memory, there are proposed a static type semiconductor memory device, a mask read only memory (MROM), a programmable read only memory (PROM), an ultra-violet programmable read only memory (UV-EPROM), an electrically erasable read only memory (EEPROM), and the like. Among them, as the EEPROM, a NAND type or NOR type flash memory is known and is widely sold.
Among technologies of those nonvolatile semiconductor memories, a technology of a general ROM is disclosed in Japanese Unexamined Patent Application Publication (JP-A) No. 2001-143490. Japanese Unexamined Patent Application Publication (JP-A) No. 2001-143490 discloses a data read assist circuit that is used when data is read from a ROM. The data read assist circuit disclosed in Japanese Unexamined Patent Application Publication (JP-A) No. 2001-143490 performs an operation of applying the same potential to selected bit lines and unselected bit lines before reading data when data is read from a ROM element selected by bit lines and a word line, and also carries out an operation of connecting the unselected bit lines to the ground after starting the actual data reading (sensing) of the selected bit lines. Thus, capacitance between the selected bit line and the unselected bit line can be reduced before reading data, and hence data can be read at high speed.
Japanese Unexamined Patent Application Publication (JP-A) No. 2002-170388 discloses a static type semiconductor memory device which can reduce interference between bit lines when memory cell data is read so that a transition speed of an amplitude on each bit line can be increased. Therefore, Japanese Unexamined Patent Application Publication (JP-A) No. 2002-170388 discloses a precharge control circuit and a bit line load circuit for maintaining even bit lines in a precharged state if memory cell data is read on odd bit lines when the memory cell is selected. In other words, potential of an adjacent bit line is charged to a high voltage from a so-called standby state before starting to access, and the potential does not change after the access.
Further, Japanese Patent Translation Publication No. 2005-537597 discloses a flash memory device in which sources and drains of memory cells are connected linearly in the row direction so as to form a linear chain, and precharging thereof. Disclosed therein is a so-called chain type cross point memory array in which gates of memory cells in the row forming the linear chain are connected to a common word line, and a column line is connected as a bit line to a node between adjacent memory cells of the linear chain. In Japanese Patent Translation Publication No. 2005-537597, the precharge is performed by applying a sensing voltage to the selected bit lines and by applying the voltage also to the bit line adjacent to the selected bit line. Thus, the application of the sensing voltage to the selected bit lines can prevent leak current flowing to the adjacent bit line through the adjacent memory cell.
In addition, Japanese Unexamined Patent Application Publication (JP-A) No. 2008-257783 discloses a nonvolatile memory device in which a plurality of memory cells are connected in series. Here, it is proposed to change drive capacity in a discontinuous access operation of a burst operation so as to reduce current consumption and access time.
On the other hand, in Japanese Patent Application No. 2009-23248, the inventor of this invention has proposed a semiconductor memory device in which a memory cell is formed of an access transistor and a nonvolatile memory element (hereinafter simply referred to as a memory element) which stores information by a resistance difference, and a method of reading the semiconductor memory device. It is confirmed that the semiconductor memory device can operate as a nonvolatile RAM. Therefore, the semiconductor memory device disclosed in Japanese Patent Application No. 2009-23248 can hold information even if the power supply is turned off. In addition, the semiconductor memory device has various other advantages which are rewritable, capable of page reading, and capable of random access similarly to a DRAM, and so on. However, according to further studies by the inventor of this invention, it has been found that further increase of speed is necessary also in a semiconductor memory device using a memory element which utilizes a resistance difference.
Japanese Unexamined Patent Application Publication (JP-A) No. 2001-143490 discloses only that a high speed operation of the ROM is achieved by applying the same potential to the selected bit line and the unselected bit line of the ROM, and does not disclose any problem that is inherent in the RAM using the memory element as disclosed in Japanese Patent Application No. 2009-23248. Further, the adjacent bit line is discharged to the original ground potential intentionally in the sensing action, which makes a noise source reducing sensitivity in sensing a micro potential by its capacitance coupling noise.
Japanese Unexamined Patent Application Publication (JP-A) No. 2002-170388 discloses only a high speed operation of the static type semiconductor device capable of random access, and does not disclose any semiconductor memory device including a memory element which utilizes a resistance difference and its problem.
Further, each of Japanese Patent Translation Publication No. 2005-537597 and Japanese Unexamined Patent Application Publication (JP-A) No. 2008-257783 discloses a rewritable, nonvolatile semiconductor memory device in which memory cells are connected linearly to form a linear chain. However, the semiconductor memory devices disclosed in Japanese Patent Translation Publication No. 2005-537597 and Japanese Unexamined Patent Application Publication (JP-A) No. 2008-257783 disclose only charging of the bit lines of the memory cells connected linearly, and do not discuss any connection relationship between the bit line and the sense amplifier.
Here, the problem of the semiconductor memory device disclosed in Japanese Patent Application No. 2009-23248 is described concretely. In the memory cell including the memory element utilizing a resistance difference, before reading stored information, the memory cell is selected and the bit line connected to the memory cell is connected to the ground so that charges are once discharged. After that, an equalizer circuit puts the memory cell into a charged state (i.e., equalized state) via the selected bit line, and then current is supplied (sensing) to the memory element that stores information by a resistance difference. A variation of potential or a variation of current caused by supplying current is read by a sense amplifier. In this case, the sense amplifier receives a potential variation due to the current flowing through the memory cell charged by the equalizer circuit, and then the potential variation is amplified so as to output the information in the state where the equalizer circuit and the bit line are electrically disconnected from the sense amplifier temporarily. In this way, it is found that a high speed operation can not be realized in the semiconductor memory device having the equalizer circuit for charging the bit line connected to the sense amplifier.
In addition, the adjacent unselected bit line is connected to the GND when the selected bit line is charged by the equalizer circuit. In this event, there is a problem that the potential of the adjacent unselected bit line is raised during the charging action. This is because a circuit connected to the GND has a portion physically far from the selected bit line and is capacitively coupled to the selected bit line. There is a problem that a discharge of this raised potential causes coupling noise which is given to the selected bit line under the sensing action.
Herein, it is assumed that the technology of applying the same potential to the selected bit line and a bit line adjacent to the selected bit line is adopted in the semiconductor memory device disclosed in Japanese Patent Application No. 2009-23248, like in Japanese Unexamined Patent Application Publication (JP-A) No. 2001-143490, Japanese Unexamined Patent Application Publication (JP-A) No. 2002-170388, Japanese Patent Translation Publication No. 2005-537597, and Japanese Unexamined Patent Application Publication (JP-A) No. 2008-257783. However, it has been found out that using the equalizer circuit disclosed in Japanese Patent Application No. 2009-23248 makes it difficult to achieve both the high speed operation and the sensing action with little error.